Application Note
78K/0 Series
8-bit Single-chip Microcontrollers Basics (II)
PD78044F Subseries PD78044H Subseries PD780208 Subseries PD780228 Subseries
Document No. U10121EJ3V0AN00 (3rd edition) Date Published August 1997 J
(c)
Printed in Japan
1993
SUMMARY OF CONTENTS
CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 CHAPTER 6 CHAPTER 7 CHAPTER 8 CHAPTER 9
OVERVIEW ....................................................................................................................... SOFTWARE BASICS ....................................................................................................... SYSTEM CLOCK SWITCHING APPLICATION .............................................................. WATCHDOG TIMER APPLICATION ............................................................................... 16-BIT TIMER/EVENT COUNTER APPLICATION .........................................................
1 15 37 51 59
8-BIT TIMER/EVENT COUNTER APPLICATION ........................................................... 101 WATCH TIMER APPLICATION ....................................................................................... 117 SERIAL INTERFACE APPLICATION ............................................................................. 127 A/D CONVERTER APPLICATION ................................................................................... 215
CHAPTER 10 APPLICATIONS OF FIP CONTROLLER/DRIVER ......................................................... 249 CHAPTER 11 APPLICATIONS OF 6-BIT UP/DOWN COUNTER .......................................................... 275 APPENDIX A SPD CHART DESCRIPTION ............................................................................................ 281 APPENDIX B REVISION HISTORY ......................................................................................................... 289
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP is a trademark of NEC Corporation. EEPROM and IEBus are trademarks of NEC Corporation.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96. 5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
Major Changes
Page Throughout Description The following products have been added as applicable products: PD78044F, PD78044H, and PD780228 subseries, PD780206, and PD780208 The following subseries have been dropped as applicable products: PD78024 and PD78044A subseries P.37, 38 P.39, 40 P.53, 54 P.128, 129 P.216, 217 P.258, 260 P.1 The following register formats and tables are described separately according to the products: Tables 3-1 and 3-2, Figures 3-1, 3-2, 4-2, 4-3, 8-1, 8-2, 9-1, 9-2, 10-7, and 10-8
The following subseries have been added in Section 1.1. PD78075B, PD78075BY, PD780018, PD780018Y, PD780058, PD780058Y, PD78058F, PD78058FY, PD780034, PD780034Y, PD780024, PD780024Y, PD78014H, PD780964, PD780924, PD780228, PD78044H, PD78044F, PD780308, PD780308Y, PD78064B, PD78098B, PD780973, PD780805 subseries, and PD78P0914 Table 3-3 has been added. Note 2 and Caution 2 have been added to Figure 4-2. Figure 4-4 has been added. A Caution has been added to Figure 5-5. Table 8-2 has been added. Note 4 and a Caution have been added to Figure 8-3. A Caution has been added to Figure 8-9. Section 8.1 The PD6252 has been defined as a product for maintenance purposes only. Figure 9-4 has been added.
P.40 P.53 P.55 P.63 P.127 P.130 P.139 P.141 P.219
The mark
shows major revised points.
[MEMO]
PREFACE
Target users
*
This application note is for engineers who wish to understand 78K/0 Series devices and design application programs using these devices. * Target products in each subseries PD78044F subseries : PD78042F, PD78043F, PD78044F, PD78045F, PD78P048A PD78044H subseries : PD78044H, PD78045H, PD78046H, PD78P048BNote PD780208 subseries : PD780204, PD780205, PD780206, PD780208, PD78P0208 PD780228 subseries : PD780226Note, PD780228Note, PD78F0228 Note Note Under development
Objective
The purpose of this application note is to use program examples to help users to understand the basic functions of 78K/0 Series devices. The program and hardware structures published here are illustrative examples and are not designed for mass production. This application note is broadly divided into the following areas. * Overview * Software * Hardware
Organization
The following application notes are supported.
Document name Document No. Japanese English 78K/0 Series Application Note, Basics (I) 78K/0 Series Application Note, Basics (II) IEA-715 IEA-1288 PD78002, 78002Y PD78014, 78014Y PD78018F, 78018FY PD78044F PD78044H PD780208 PD780228 Describes basic functions of 78K/0 Series products, using program examples. Applicable subseries Description
U10121J This manual
78K/0 Series Application Note, Basics (III)
IEA-767
U10182E PD78054, 78054Y PD78064, 78064Y PD78078, 78078Y PD78083 PD78098 IEA-1289 All subseries of 78K/0 Series Except for PD78002 and PD78002Y subseries IEA-1301 PD78014 Only the PD78014 and PD78P014 are applicable. Describes the floating-point operation application programs of 78K/0 Series products. Describes the functions and configuration of electronic notes, using PD78014 subseries products as examples.
78K/0 Series Application IEA-718 Note, Floating-Point Operation Program PD78014 Series Application IEA-744 Note, Electronic Notes
Caution In this application note, the application examples and program listings are written for the main system clock operating at 4.19 MHz. They are not for the main system clock operating at 5.0 MHz.
Reading this note This application note is for 78K/0 Series products, but each subseries has different functions. Each subseries is described in the chapters listed in the following table. Sample applications for each subseries are given in those chapters indicated by circles.
Subseries Chapter Chapter 1 Overview Chapter 2 Software Basics Chapter 3 System Clock Switching Application Chapter 4 Watchdog Timer Application Chapter 5 16-bit Timer/Event Counter Application Chapter 6 8-bit Timer/Event Counter Application Chapter 7 Watch Timer Application Chapter 8 Serial Interface Application Chapter 9 A/D Converter Application Chapter 10 Applications of FIP Controller/Driver Chapter 11 Applications of 6-bit Up/Down Counter PD78044F o o o o o o o o o o o PD78044H o o o o o o o o o o PD780208 o o o o o o o o o o PD780228 o o o o o o -
Legend
Significance of the : data description Active-low description : Note : Caution : Remark : Number descriptions :
The left side is high-order data and the right side is low-order data. xxx (line above pin and signal names) Explanation of the note attached to the text. Contents that should be read carefully Supplemental explanation of the text Binary numbers ............. xxxx or xxxxB Decimal numbers .......... xxxx Hexadecimal numbers .. xxxxH
Application area
* Consumer product field
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Common documents
Document number Document name Japanese 78K/0 Series Application Note, Basics (II) 78K/0 Series User's Manual, Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table U10121J U12326J U10904J U10903J English This manual IEU-1372 -
* Documents for PD78044F subseries
Document number Japanese PD78042F, 78043F, 78044F, 78045F Data Sheet PD78P048A Data Sheet PD78044F Subseries User's Manual PD78044A, 78044F Subseries Special Function Register Table U10700J U10611J U10908J U10701J English U10700E U10611E U10908E -
Document name
**
Documents for PD78044H subseries
Document number Japanese PD78044H, 78045H, 78046H Data Sheet PD78P048B Data Sheet PD78044H Subseries User's Manual U10865J To be created U11756J English U10865E To be created U11756E
Document name
* Documents for PD780208 subseries
Document number Japanese PD780204, 780205, 780206, 780208 Data Sheet PD78P0208 Data Sheet PD780208 Subseries User's Manual PD780208 Subseries Special Function Register Table U10436J U11295J U11302J U10997J English U10436E U11295E U11302E -
Document name
*
* Documents for PD780228 subseries
Document number Japanese PD780226, 780228 Data Sheet PD78F0228 Preliminary Product Information PD780228 Subseries User's Manual U11797J U11971J U12012J English U11797E U11971E U12012E
Document name
The above documents may be revised without notice. Use the latest versions when you design an application system.
[MEMO]
CONTENTS
CHAPTER 1
OVERVIEW ....................................................................................................................... 1.1 1.2 78K/0 SERIES PRODUCT DEVELOPMENT ......................................................... 78K/0 SERIES FEATURES ....................................................................................
1 1 3
CHAPTER 2
SOFTWARE BASICS ....................................................................................................... 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 DATA TRANSFER ................................................................................................... DATA COMPARISON.............................................................................................. DECIMAL ADDITION .............................................................................................. DECIMAL SUBTRACTION ...................................................................................... BINARY-TO-DECIMAL CONVERSION .................................................................. BIT OPERATION MANIPULATION INSTRUCTION .............................................. BINARY MULTIPLICATION (16 BITS x 16 BITS) .................................................. BINARY DIVISION (32 BITS/16 BITS) ...................................................................
15 15 16 17 24 26 28 29 33
CHAPTER 3
SYSTEM CLOCK SWITCHING APPLICATION .............................................................. 3.1 3.2 SWITCHING PCC AFTER RESET ......................................................................... SWITCHING DURING POWER ON/OFF ...............................................................
37 46 47
CHAPTER 4
WATCHDOG TIMER APPLICATION ............................................................................... 4.1 4.2 SETTING THE WATCHDOG TIMER MODE ......................................................... INTERVAL TIMER MODE SETTING ......................................................................
51 56 58
CHAPTER 5
16-BIT TIMER/EVENT COUNTER APPLICATION ......................................................... 5.1 5.2 5.3 INTERVAL TIMER SETTING .................................................................................. PWM OUTPUT ........................................................................................................ REMOTE CONTROL RECEPTION ........................................................................ 5.3.1 5.3.2 Remote Control Reception by a Counter Clear ........................................ Remote Control Reception by PWM Output and Free Running ..............
59 65 67 69 72 86
-i-
CHAPTER 6
8-BIT TIMER/EVENT COUNTER APPLICATION ........................................................... 101 6.1 SETTING THE INTERVAL TIMER ......................................................................... 106 6.1.1 6.1.2 6.2 Setting an 8-Bit Timer ................................................................................ 107 Setting the 16-Bit Timer ............................................................................. 109
MUSICAL SCALE GENERATION ........................................................................... 111
CHAPTER 7
WATCH TIMER APPLICATION ....................................................................................... 117 7.1 WATCH AND LED DISPLAY PROGRAM .............................................................. 119
CHAPTER 8
SERIAL INTERFACE APPLICATION ............................................................................. 127 8.1 8.2 8.3 INTERFACING WITH EEPROMTM (PD6252) ...................................................... 141 8.1.1 Communication in the 2-Wire Serial I/O Mode ......................................... 143 INTERFACING WITH THE OSD LSI (PD6451A) ................................................ 153 SBI MODE INTERFACE ......................................................................................... 158 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.5 8.5.1 8.5.2 Application as a Master CPU .................................................................... 160 Application as a Slave CPU ....................................................................... 169 Application as a Master CPU .................................................................... 174 Application as a Slave CPU ....................................................................... 178 Half-Duplex Asynchronous Communication of the 3-Wire Mode ............. 182 Half-Duplex Asynchronous Communication in the SBI Mode .................. 197
3-WIRE SERIAL I/O MODE INTERFACE .............................................................. 173
HALF-DUPLEX ASYNCHRONOUS COMMUNICATION ....................................... 182
CHAPTER 9
A/D CONVERTER APPLICATION ................................................................................... 215 9.1 9.2 9.3 9.4 LEVEL METER ........................................................................................................ 220 THERMOMETER ..................................................................................................... 229 ANALOG KEY INPUT .............................................................................................. 239 4-CHANNEL INPUT A/D CONVERSION ............................................................... 245
CHAPTER 10 APPLICATIONS OF FIP CONTROLLER/DRIVER ......................................................... 249 10.1 12-DIGIT DISPLAY FOR FIP AND KEY INPUT .................................................... 262 10.1.1 12-Digit FIP Display ................................................................................... 263 10.1.2 Key Input .................................................................................................... 266 10.1.3 Description of Package .............................................................................. 268 10.1.4 Example of Use .......................................................................................... 270 10.1.5 SPD Chart .................................................................................................. 272 10.1.6 Program Listing .......................................................................................... 273 - ii -
CHAPTER 11 APPLICATIONS OF 6-BIT UP/DOWN COUNTER ......................................................... 275 11.1 1-SECOND COUNTER ........................................................................................... 277
APPENDIX A SPD CHART DESCRIPTION ........................................................................................... 281
APPENDIX B REVISION HISTORY ........................................................................................................ 289
- iii -
LIST OF FIGURES (1/4)
Figure No. 1-1. 1-2. 1-3. 1-4. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 4-1. 4-2. 4-3. 4-4. 4-5. 5-1. 5-2. Title Page 4 7 10 13 15 16 17 24 26 28 29 33
Block Diagram of the PD78044F Subseries .................................................................. Block Diagram of the PD78044H Subseries .................................................................. Block Diagram of the PD780208 Subseries .................................................................. Block Diagram of the PD780228 Subseries .................................................................. Data Exchange .................................................................................................................. Data Comparison .............................................................................................................. Decimal Addition ............................................................................................................... Decimal Subtraction .......................................................................................................... Binary-to-Decimal Conversion .......................................................................................... Bit Operation ...................................................................................................................... Binary Multiplication .......................................................................................................... Binary Division ................................................................................................................... Format of the Processor Clock Control Register (PD78044F, PD78044H, and PD780208 Subseries) ................................................ Format of the Processor Clock Control Register (PD780228 Subseries) .................... Format of the Display Mode Register 0 (PD78044F and PD78044H Subseries) ...... Format of the Display Mode Register 0 (PD780208 Subseries)................................... Format of the Display Mode Register 1 (PD78044F and PD78044H Subseries) ...... Format of the Display Mode Register 1 (PD780208 Subseries)................................... CPU Clock Switching after RESET (PD78044F Subseries) ......................................... Example of the System Clock Switching Circuit .............................................................. System Clock Switching during Power On and Off (PD78044F Subseries) ................ Format of Timer Clock Selection Register 2 (PD78044F, PD78044H, and PD780208 Subseries) ................................................ Format of the Watchdog Timer Mode Register (PD78044F, PD78044H, and PD780208 Subseries) ................................................ Format of the Watchdog Timer Mode Register (PD780228 Subseries) ....................... Format of the Watchdog Timer Clock Selection Register (Only for the PD780228 Subseries) ............................................................................... Count Timing of the Watchdog Timer .............................................................................. Format of Timer Clock Selection Register 0 .................................................................... Format of the 16-Bit Timer Mode Control Register .........................................................
39 40 41 42 44 45 46 47 48
52 53 54 55 58 60 61
- iv -
LIST OF FIGURES (2/4)
Figure No. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 5-10. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 7-1. 7-2. 7-3. 7-4. 7-5. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. Title Page 62 63 63 64 69 70 71 72
Format of the 16-Bit Timer Output Control Register ....................................................... Format of the Port Mode Register 3................................................................................. Format of the External Interrupt Mode Register .............................................................. Format of the Sampling Clock Selection Register ........................................................... Example of the Remote Control Receiving Circuit .......................................................... IC Output Signal for Remote Control Transmission ........................................................ Output Signal of the Receiving Preamplifier .................................................................... Sampling the Remote Control Signal ...............................................................................
Format of Timer Clock Selection Register 1 .................................................................... 102 Format of the 8-Bit Timer Mode Control Register ........................................................... 103 Format of the 8-Bit Timer Output Control Register ......................................................... 104 Format of Port Mode Register 3 ....................................................................................... 105 Count Timing of an 8-Bit Timer ........................................................................................ 106 Musical Scale Generation Circuit ..................................................................................... 111 Timer Output and Interval ................................................................................................. 111 Format of Timer Clock Selection Register 2 .................................................................... 117 Format of the Watch Timer Mode Control Register ........................................................ 118 Schematic of Watch Data ................................................................................................. 119 LED Display Timing ........................................................................................................... 120 Example Circuit of the Watch Timer ................................................................................ 120 Format of Timer Clock Selection Register 3 (PD78044F and PD780208 Subseries) ........................................................................ 128 Format of Timer Clock Selection Register 3 (PD78044H Subseries) .......................... 129 Format of Serial Operating Mode Register 0 (Only for the PD78044F and PD780208 Subseries) ................................................... 130 Format of the Serial Operating Mode Register 1 ............................................................ (PD78044F and PD780208 Subseries) ........................................................................ 132 Format of the Serial Operating Mode Register 1 (PD78044H Subseries) ................... 133 Format of the Interrupt Timing Setting Register (Only for the PD78044F and D780208 Subseries)...................................................... 134 Format of the Serial Bus Interface Control Register (Only for the PD78044F and PD780208 Subseries) ................................................... 135 Format of the Automatic Data Transmit/Receive Control Register (Only for the PD78044F and PD780208 Subseries) ................................................... 137 -v-
LIST OF FIGURES (3/4)
Figure No. 8-9. 8-10. 8-11. 8-12. 8-13. 8-14. 8-15. 8-16. 8-17. 8-18. 8-19. 8-20. 8-21. 8-22. 8-23. 8-24. 8-25. 8-26. 8-27. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. Title Page
Format of the Automatic Data Transmit/Receive Interval Setting Register (Only for the PD78044F and PD780208 Subseries) ................................................... 138 PD6252 Pin Configuration .............................................................................................. 141 PD6252 Connection Example......................................................................................... 143 PD6252 Communication Format .................................................................................... 145 Connection Example with PD6451A .............................................................................. 153 PD6451A Communication Format .................................................................................. 153 Connection Example of the SBI Mode ............................................................................. 158 SBI Mode Communication Format ................................................................................... 159 Timed Out ACK Signal ...................................................................................................... 160 Bus Line Test .................................................................................................................... 160 Connection Example of the 3-Wire Serial I/O Mode ....................................................... 173 Communication Format of the 3-Wire Serial I/O Mode ................................................... 173 Busy Signal Output ........................................................................................................... 178 System Structure (3-Wire Mode) ...................................................................................... 182 3-Wire Mode Transmission Format .................................................................................. 183 3-Wire Mode Reception Format ....................................................................................... 184 System Structure (SBI Mode) ........................................................................................... 197 SBI Mode Transmission Format ....................................................................................... 198 SBI Mode Reception Format ............................................................................................ 199 Format of the A/D Converter Mode Register (PD78044F, PD78044H, and PD780208 Subseries) ................................................ 216 Format of the A/D Converter Mode Register (PD780228 Subseries) .......................... 217 Format of the A/D Converter Input Selection Register (PD78044F, PD78044H, and PD780208 Subseries) ................................................ 218 Format of the Analog Input Channel Specification Register (Only for the PD780228 Subseries) ............................................................................... 219 Level Meter Circuit Example ............................................................................................. 220 A/D Conversion Result and LED Display ......................................................................... 220 Conceptual Diagram of the Peak Hold ............................................................................. 221 Thermometer Circuit Example .......................................................................................... 229 Temperature and Output Characteristics ......................................................................... 230 Analog Key Input Circuit Example .................................................................................... 240 Timing Chart in the 4-Channel Scanning Mode ............................................................... 245
- vi -
LIST OF FIGURES (4/4)
Figure No. 10-1. 10-2. 10-3. 10-4. 10-5. 10-6. 10-7. 10-8. 10-9. 10-10. 10-11. 10-12. 10-13. 10-14. 10-15. 11-1. 11-2. Title Page
Format of Display Mode Register 0 (PD78044F and PD78044H Subseries) ............ 251 Format of Display Mode Register 0 (PD780208 Subseries) ......................................... 252 Format of Display Mode Register 0 (PD780228 Subseries) ......................................... 254 Format of Display Mode Register 1 (PD78044F and PD78044H Subseries) ............ 255 Format of Display Mode Register 1 (PD780208 Subseries) ......................................... 256 Format of Display Mode Register 1 (PD780228 Subseries) ......................................... 257 Format of Display Mode Register 2 (PD780208 Subseries) ......................................... 258 Format of Display Mode Register 2 (PD780228 Subseries) ......................................... 260 FIP Controller Operation Timing ....................................................................................... 261 Configuration of 12-Digit FIP Display and Key Input ....................................................... 262 Pin Layout for 9-Segment Display .................................................................................... 264 Relationship between Contents of Display Data Memory and Segment Output ........... 265 Display Example ................................................................................................................ 266 Key Interrupt Timing Chart ............................................................................................... 267 Compensating for Chattering ............................................................................................ 268 Block Diagram of 6-Bit Up/Down Counter ....................................................................... 275 Format of 6-Bit Up/Down Counter Control Register ........................................................ 276
- vii -
LIST OF TABLES
Table No. 1-1. 1-2. 1-3. 1-4. 3-1. 3-2. 3-3. 5-1. 5-2. 6-1. 8-1. 8-2. 8-3. 8-4. 8-5. 9-1. 9-2. 9-3. 10-1. Title Page 5 8 11 14
Function Overview of the PD78044F Subseries............................................................ Function Overview of the PD78044H Subseries ........................................................... Function Overview of the PD780208 Subseries ............................................................ Function Overview of the PD780228 Subseries ............................................................ Maximum Time Required to Change the CPU Clock (PD78044F, PD78044H, and PD780208 Subseries) ................................................ Maximum Time Required to Change the CPU Clock (PD780228 Subseries) ............. Relationship between the CPU Clock and Minimum Instruction Execution Time .......... Valid Time for Input Signal ............................................................................................... Valid Time of the Input Signal ..........................................................................................
37 38 40 72 86
Musical Scale and Frequencies ........................................................................................ 112 Available Serial Interface Channels in Each Subseries .................................................. 127 Serial Interface Registers ................................................................................................. 127 Description of PD6252 Pins............................................................................................ 142 PD6252 Command List ................................................................................................... 144 SBI Mode Signal List ......................................................................................................... 159 A/D Conversion Values and Temperatures ..................................................................... 231 Input Voltages and Key Codes ......................................................................................... 239 Resistances of R1 to R15 ................................................................................................. 240 Differences between PD78044F, PD78044H, PD780208, and PD780228 Subseries ...................................................................................................... 250 Comparison of SPD Symbols and Flowcharts ................................................................. 281
A-1.
- viii -
CHAPTER 1 OVERVIEW
CHAPTER 1 OVERVIEW
*
1.1 78K/0 SERIES PRODUCT DEVELOPMENT The 78K/0 series products were developed as shown below. The subseries names are indicated in frames.
Products currently being mass-produced Products under development Used for control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin Y subseries products are compatible with the I2C bus. EMI noise-reduced versions of the PD78078 A timer has been added to the PD78054 to enhance its external interface functions. ROM-less versions of the PD78078 The serial I/O of the PD78078Y has been enhanced by limiting its functions Serial I/O of the PD78054 has been enhanced. EMI noise-reduced versions of the PD78054 EMI noise-reduced versions of the PD78054 A UART and D/A converter have been added to the PD78014 to enhance its I/O. The A/D converter of the PD780024 has been enhanced. The serial I/O of the PD78018F has been enhanced. EMI noise-reduced versions of the PD78018F. EMI noise-reduced version of the PD78018F Low-voltage (1.8 V) versions of the PD78014. ROM and RAM variations have been enhanced. An A/D converter and 16-bit timer have been added to the PD78002. An A/D converter has been added to the PD78002. Basic subseries for control This product includes a UART and can operate at a low voltage (1.8 V).
PD78075B PD78075BY PD78078 PD78078Y PD78070A PD78070AY PD780018AY PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 PD780024Y PD78014H PD78018F PD78018FY PD78014 PD78014Y PD780001 PD78002 PD78002Y PD78083
For inverter control
64-pin 64-pin 78K/0 Series 100-pin 100-pin 80-pin 80-pin
PD780964 PD780924
For FIPTM driving
An A/D converter of the PD780924 has been enhanced. This product includes an inverter control circuit and UART. EMI noise-reduced version. The I/O and the FIP controller/driver of the PD78044F have been enhanced. Total indication output pins: 53 The I/O and the FIP controller/driver of the PD78044H have been enhanced. Total indication output pins: 48 N-ch open-drain I/O pins have been added to the PD78044F. Total indication output pins: 34 Basic subseries for FIP driving. Total indication output pins: 34
PD780208 PD780228 PD78044H PD78044F
For LCD driving
100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
PD780308Y PD78064Y
SIO of the PD78064 has been enhanced. ROM and RAM have been extended. EMI noise-reduced version of the PD78064 Basic subseries for LCD driving. These products include a UART.
Compatible with IEBusTM 80-pin 80-pin
PD78098B PD78098
EMI noise-reduced version of the PD78098 An IEBus controller has been added to the PD78054.
For meter control 80-pin
PD780973
This product includes a controller/driver for driving car meters.
For LV 64-pin
PD78P0914
This product includes the PWM output, LV digital code decoder, and Hsync counter.
Note Being planned
1
78K/0 SERIES APPLICATION NOTE
The table below shows the main differences between subseries.
Function Subseries name PD78075B PD78078 PD78070A PD780058 PD78058F For control PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
For inverter control
ROM capacity 32K-40 K 48K-60K 24K-60K 48K-60K 16K-60K 8K-32K 2 ch
Timer 8-bit 16-bit Watch WDT 4 ch 1 ch 1 ch 1 ch
8-bit 10-bit A/D 8 ch A/D -
8-bit D/A 2 ch
Serial interface
I/O
Minimum External VDD expansion o
3 ch (UART: 1 ch) 88 pins
1.8 V
61 pins 2 ch 3ch (time-multiplexing 68 pins UART: 1ch) 3 ch (UART: 1 ch) 69 pins
2.7 V 1.8 V 2.7 V 2.0 V
8 ch
8 ch -
-
3 ch (UART: 1 ch, time- 51 pins multiplexing 3-wire: 1ch) 2 ch 53 pins
1.8 V
8K-60K 8K-32K 8K 8K-16K 1 ch 8K-32K 3 ch Note 1 ch 8 ch 8 ch 32K-60K 48K-60K 32K-48K 16K-40K 48K-60K 32K 16K-32K 40K-60K 32K-60K 24K-32K 3 ch 1 ch 1 ch 1 ch 5 ch 2 ch (UART: 1 ch) 56 pins 4.5 V 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (UART: 1 ch) 69 pins 2.7 V o 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch 2 ch 1 ch 1 ch 1 ch 1 ch 1 ch 2 ch 3ch (time-multiplexing 57 pins UART: 1ch) 2 ch (UART: 1 ch) 2.0 V 8 ch 8 ch 2 ch 1 ch 74 pins 72 pins 68 pins 2.7 V 4.5 V 2.7 V 1 ch 39 pins 53 pins 1 ch (UART: 1 ch) 33 pins 2 ch (UART: 2 ch) 47 pins 1.8 V 2.7 V 2.7 V o o
PD780964 PD780924 PD780208 PD780228 PD78044H PD78044F PD780308 PD78064B PD78064 PD78098B PD78098 PD780973
For meter Compatible For LV control with IEBus
For LCD driving For FIP driving
PD78P0914
32K
6 ch
-
-
1 ch
8 ch
-
-
2 ch
54 pins
4.5 V
o
Note 10-bit timer: 1 channel
2
CHAPTER 1 OVERVIEW
1.2 78K/0 SERIES FEATURES The 78K/0 Series devices are 8-bit single-chip microcontrollers ideally suited for applications in the consumer field. The PD78044F subseries are devices that implement high-speed, high-performance CPUs and have on-chip peripheral hardware, such as ROM, RAM, I/O ports, timers, serial interfaces, A/D converter, FIP controller/driver, 6-bit up/down counter, and interrupt controllers. The PD78044H subseries of devices has been implemented by adding N-ch open-drain I/O pins to the PD78044F subseries. The PD780208 subseries has an enhanced version of the FIP controller/driver of the PD78044F subseries. The PD780228 subseries has an enhanced version of the FIP controller/driver of the PD78044H subseries. The one-time PROM or EPROM versions or flash memory version, that can operate at the same low voltage as mask ROM versions, such as the PD78P048A, PD78P048B, PD78P0208, and PD78F0228 are also provided. These products are well suited for fast shift to production of application systems and small-lot production. A block diagram and an overview of the functions of each subseries are shown on the following pages.
* *
*
3
78K/0 SERIES APPLICATION NOTE
Figure 1-1. Block Diagram of the PD78044F Subseries
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0
P00 P01-P03 P04 P10-P17
8-bit TIMER/ EVENT COUNTER1 8-bit TIMER/ EVENT COUNTER2
PORT1
PORT2
P20-P27
WATCHDOG TIMER
PORT3
P30-P37
WATCH TIMER 6-bit UP/DOWN COUNTER 78K/0 CPU CORE ROM
PORT7
P70-P74
CI0/INTP3/P03 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/CI0/P03 BUZ/P36
PORT8
P80, P81
SERIAL INTERFACE 0
PORT9
P90-P97
PORT10 SERIAL INTERFACE 1
P100-P107
PORT11
P110-P117
PORT12 RAM FIP CONTROLLER/ DRIVER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL
P120-P127
A/D CONVERTER
FIP0-FIP33 VLOAD
SYSTEM CONTROL VDD VSS IC (VPP)
PCL/P35
RESET X1 X2 XT1/P04 XT2
Remarks 1. The capacities of the internal ROM and RAM differ depending on the product. 2. The value enclosed in parentheses is applied to the PD78P048A.
4
CHAPTER 1 OVERVIEW
*
Item Internal memory ROM
Table 1-1. Function Overview of the PD78044F Subseries (1/2)
Product name PD78042F Masked ROM 16K bytes High-speed RAM Extended RAM Buffer RAM FIP display RAM General-purpose registers
Minimum instruction execution time
PD78043F
PD78044F
PD78045F
PD78P048A
One-time PROM/EPROM
24K bytes
32K bytes 1024 bytes -
40K bytes
60K bytes Note 1 1024 bytesNote 2 1024 bytes
512 bytes
64 bytes 48 bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) 122 s (at 32.768 kHz) * 16-bit operations * Multiplication/division (8 bits x 8 bits, 16 bits/8 bits) * Bit (set, reset, test, Boolean operations) * BCD conversion, etc.
For main system clock For subsystem clock
Instruction set
I/O ports (including those multiplexed with FIP pins)
* Total * CMOS input * CMOS I/O * N-ch open-drain I/O * P-ch open-drain I/O
: 68 pins : 2 pins : 27 pins : 5 pins : 16 pins
* P-ch open-drain output : 18 pins FIP controller/driver * Total : 34 pins
* Segments : 9 to 24 pins * Digits A/D converter : 2 to 16 pins
* 8-bit resolution x 8 channels * Power supply voltage: AVDD = 4.0 to 6.0 V
Serial interface
* 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel
Timer
* 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer * Watchdog timer * 6-bit up/down counter : 1 channel : 1 channel : 1 channel
Timer outputs
3 (one for 14-bit PWM output)
Notes 1. The memory size switching register (IMS) can be used to select 16K, 24K, 32K, 40K, or 60K bytes. 2. The IMS can be used to select 512K or 1024K bytes.
5
78K/0 SERIES APPLICATION NOTE
Table 1-1. Function Overview of the PD78044F Subseries (2/2)
Product name Item Clock output PD78042F PD78043F PD78044F PD78045F PD78P048A
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz)
Buzzer output Vectored interrupt factors Maskable Non-maskable Software Test input Power supply voltage Package
1.2 kHz, 2.4 kHz, 4.9 kHz (at 5.0 MHz: main system clock) Internal: 10, external: 4 Internal: 1 1 Internal: 1 VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 20 mm) * 80-pin ceramic WQFN: Only for the PD78P048A
6
CHAPTER 1 OVERVIEW
*
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
Figure 1-2. Block Diagram of the PD78044H Subseries
16-bit TIMER/ EVENT COUNTER
PORT0
P00 P01-P03 P04 P10-P17
8-bit TIMER/ EVENT COUNTER1 8-bit TIMER/ EVENT COUNTER2
PORT1
PORT2
P20-P27
WATCHDOG TIMER
PORT3
P30-P37
WATCH TIMER 6-bit UP/DOWN COUNTERNote 78K/0 CPU CORE ROM
PORT7
P70-P74
CI0/INTP3/P03 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB /P23 BUSYNote/P24
Note
PORT8
P80, P81
SERIAL INTERFACE 0Note
PORT9
P90-P97
PORT10 SERIAL INTERFACE 1
P100-P107
PORT11
P110-P117
PORT12 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/CI0/P03 BUZ/P36 RAM FIP CONTROLLER/ DRIVER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL
P120-P127
A/D CONVERTER
FIP0-FIP33 VLOAD
SYSTEM CONTROL VDD VSS IC (VPP)
PCL/P35
RESET X1 X2 XT1/P04 XT2
Note Only for the PD78P048B Remarks 1. The capacities of the internal ROM and RAM differ depending on the product. 2. The value enclosed in parentheses is applied to the PD78P048B.
7
78K/0 SERIES APPLICATION NOTE
*
Item Internal memory ROM
Table 1-2. Function Overview of the PD78044H Subseries (1/2)
Product name PD78044H Masked ROM 32K bytes High-speed RAM Extended RAM Buffer RAM FIP display RAM General-purpose register
Minimum For main system clock instruction execution time For subsystem clock
PD78045H
PD78046H
PD78P048BNote 1 One-time PROM/EPROM
40K bytes
48K bytes
60K bytes Note 2
1024 bytes 48 bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) 122 s (at 32.768 kHz) * 16-bit operations * Multiplication/division (8 bits x 8 bits, 16 bits/8 bits) * Bit manipulations (set, reset, test, Boolean operations) * BCD conversion, etc. 1024 bytesNote 3 64 bytes
Instruction set
I/O (including those multiplexed with FIP pins)
* Total * CMOS input * CMOS I/O * N-ch open-drain I/O * P-ch open-drain I/O
: 68 lines ports : 2 lines : 19 lines : 13 lines : 16 lines
* P-ch open-drain output : 18 lines FIP controller/driver * Total : 34 lines
* Segments: 9 to 24 lines * Digits A/D converter : 2 to 16 lines * 8-bit resolution x 8 channels * Power supply voltage: AVDD = 4.0 to 6.0 V Serial interface * 3-wire serial I/O mode: 1 channel * 3-wire serial I/O, SBI, or 2-wire serial I/O mode: 1 channel
* 8-bit resolution x 8 channels * Power supply voltage: AVDD = 4.0 to 5.5 V
*
3-wire serial I/O mode with automatic transmission/reception function: 1 channel
Notes 1. Under development 2. The memory size switching register (IMS) can be used to select 32K, 40K, 48K, or 60K bytes. 3. The internal extended RAM size switching register (IXS) can be used to select 0 or 1024 bytes.
8
CHAPTER 1 OVERVIEW
Table 1-2. Function Overview of the PD78044H Subseries (2/2)
Product name Item Timer PD78044H PD78045H PD78046H PD78P048BNote * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel * 6-bit up/down counter: 1 channel Timer outputs Clock output 3 lines (one for 14-bit PWM output) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz) Buzzer output Vectored interrupt factors Software Test input Power supply voltage Package 1 Internal: 1 VDD = 2.7 to 5.5 V * 80-pin plastic QFP (14 x 20 mm) VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 20 mm) * 80-pin ceramic WQFN Maskable Non-maskable 1.2 kHz, 2.4 kHz, 4.9 kHz (at main system clock of 5.0 MHz) Internal: 8, External: 4 Internal: 1 Internal: 10, External: 4
* 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer * Watchdog timer : 1 channel : 1 channel
Note Under development
9
78K/0 SERIES APPLICATION NOTE
Figure 1-3. Block Diagram of the PD780208 Subseries
TO0/P30 TI0/INTP0/P00
16-bit TIMER/ EVENT COUNTER
PORT0
P00 P01-P03 P04 P10-P17
TO1/P31 TI1/P33 TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER1
PORT1
8-bit TIMER/ EVENT COUNTER2
PORT2
P20-P27
PORT3 WATCHDOG TIMER PORT7 WATCH TIMER PORT8 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE 0 78K/0 CPU CORE ROM
P30-P37
P70-P74
P80-P87
PORT9
P90-P97
SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/P03 BUZ/P36 SERIAL INTERFACE 1
PORT10
P100-P107
PORT11
P110-P117
PORT12 RAM FIP CONTROLLER/ DRIVER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL
P120-P127
A/D CONVERTER
FIP0-FIP52 VLOAD
SYSTEM CONTROL VDD VSS IC (VPP)
PCL/P35
RESET X1 X2 XT1/P04 XT2
Remark 1. The capacities of the internal ROM and RAM differ depending on the product. 2. The value enclosed in parentheses is applied to the PD78P0208.
10
CHAPTER 1 OVERVIEW
Table 1-3. Function Overview of the PD780208 Subseries (1/2)
Product name PD780204 Masked ROM 32K bytes High-speed RAM Extended RAM Buffer RAM FIP display RAM General-purpose registers
Minimum instruction execution time
*
Item Internal memory ROM
PD780205
PD780206
PD780208
PD78P0208
One-time PROM/EPROM
40K bytes
48K bytes
60K bytes
60K bytes Note 1
1024 bytes 64 bytes 80 bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) 122 s (at 32.768 kHz) * 16-bit operations * Multiplication/division (8 bits x 8 bits, 16 bits/8 bits) * Bit (set, reset, test, Boolean operations) * BCD conversion, etc. 1024 bytes 1024 bytesNote 2
For main system clock For subsystem clock
Instruction set
I/O ports (including those multiplexed with FIP pins)
* Total * CMOS input * CMOS I/O * N-ch open-drain I/O * P-ch open-drain I/O
: 74 pins : 2 pins : 27 pins : 5 pins : 24 pins
* P-ch open-drain output : 16 pins FIP controller/driver * Total : 53 pins
* Segments : 9 to 40 pins * Digits A/D converter : 2 to 16 pins
* 8-bit resolution x 8 channels * Power supply voltage: AVDD = 4.0 to 5.5 V
Serial interface
* 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable : 1 channel * 3-wire mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel
Timer
* 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer * Watchdog timer : 1 channel : 1 channel
Timer outputs
3 (one for 14-bit PWM output)
Notes 1. The memory size switching register (IMS) can be used to select 32K, 40K, 48K, or 60K bytes. 2. The internal extended RAM size switching register (IXS) can be used to select either 0 or 1024 bytes.
11
78K/0 SERIES APPLICATION NOTE
Table 1-3. Function Overview of the PD780208 Subseries (2/2)
Product name Item Clock output PD780204 PD780205 PD780206 PD780208 PD78P0208
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (at main system clock of 5.0 MHz) 32.768 kHz (at subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz (at 5.0 MHz: main system clock) Maskable Non-maskable Software Internal: 9, external: 4 Internal: 1 1 Internal: 1 VDD = 2.7 to 5.5 V * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN: Only for the PD78P0208
Buzzer output Vectored interrupt factors Text input Power supply voltage Package
12
CHAPTER 1 OVERVIEW
*
TI1/P23
Figure 1-4. Block Diagram of the PD780228 Subseries
8-bit REMOTE CONTROLLER TIMER (TM1)
PORT0 PORT1 PORT2
P00, P01 P10-P17 P20-P25 P40-P47 P50-P57 P60-P67 P70-P77 P80-P87 P90-P97 P100-P107 FIP0-FIP47 VLOAD RESET X1 X2
TIO50/P24
8-bit PWM TIMER (TM50) 78K/0 CPU CORE
PORT4 ROM FLASH MEMORY PORT5 PORT6 PORT7 PORT8 RAM 1024 Bytes PORT9 PORT10
TIO51/P25
8-bit PWM TIMER (TM51) WATCHDOG TIMER
SCK/P20 SO/P21 SI/P22 ANI0/P10ANI7/P17 AVDD AVSS
SERIAL INTERFACE (SIO3)
A/D CONVERTER (A/D1)
FIP CONTROLLER/ DRIVER
INTP0/P00 INTP1/P01
INTERRUPT CONTROL (INT)
VDD0, VDD1, VDD2
VSS0, VSS1
IC (VPP)
SYSTEM CONTROL
Remarks 1. The internal ROM capacity differs depending on the product. 2. The value in parentheses applies to the PD78F0228 only.
13
78K/0 SERIES APPLICATION NOTE
*
Item Internal memory ROM
Table 1-4. Function Overview of the PD780228 Subseries
Product name PD780226 Masked ROM 48K bytes High-speed RAM Extended RAM FIP display RAM General-purpose registers Minimum instruction execution time Instruction set 1024 bytes 512 bytes 96 bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at main system clock of 5.0 MHz) * 16-bit operations * Multiplication/division (8 bits x 8 bits, 16 bits/8 bits) * Bit (set, reset, test, Boolean operations) * BCD conversion, etc. I/O ports (including those multiplexed with FIP pins) * Total * CMOS input * CMOS I/O * N-ch open-drain I/O * P-ch open-drain I/O : 72 pins : 8 pins : 16 pins : 16 pins : 24 pins 60K bytes PD780228 PD78F0228 Flash memory 60K bytesNote
* P-ch open-drain output : 8 pins FIP controller/driver * Total : 48 pins
* 10-mA display current : 16 pins * 3-mA display current : 32 pins A/D converter * 8-bit resolution x 8 channels * Power supply voltage: AVDD = 4.5 to 5.5 V Serial interface Timer * 3-wire serial I/O mode: 1 channel * 8-bit remote controller timer : 1 channel * 8-bit PWM timer * Watchdog timer Timer outputs Vectored interrupt factors Software Power supply voltage Package 1 VDD = 4.5 to 5.5 V 100-pin plastic QFP (14 x 20 mm) Maskable Non-maskable 2 (8-bit PWM output enabled) Internal: 6, external: 4 Internal: 1 : 2 channels : 1 channel
Note The memory size switching register (IMS) can be used to select 48K or 60K bytes. Caution The PD780228 subseries is under development.
14
CHAPTER 2 SOFTWARE BASICS
CHAPTER 2 SOFTWARE BASICS
2.1 DATA TRANSFER The addresses set in the DE and HL registers are the first addresses used in data exchange. The number of bytes in the data exchange is specified in the B register. Figure 2-1. Data Exchange
Address DE+B-1 Address HL+B-1
Data exchange
DE
HL
(1) Registers used A, B, DE, HL (2) Program listing EXCH: MOV XCH XCH INCW INCW DBNZ RET A,[DE] A,[HL] A,[DE] DE HL B,$EXCH
15
78K/0 SERIES APPLICATION NOTE
2.2 DATA COMPARISON The addresses set in the DE and HL registers are the first addresses used in data comparison. The number of bytes in the data comparison is specified in the B register. When the comparison result is equal, the CY flag is set to 0. When the result is not equal, CY is set to 1. After the flag setting, processing is returned to the main program. Figure 2-2. Data Comparison
Address DE+B-1 Address HL+B-1
Data comparison
DE
HL
(1) Registers used A, B, DE, HL (2) Program listing COMP: MOV CMP BNZ INCW INCW DBNZ CLR1 BR ERROR: SET1 RTN: RET CY A,[DE] A,[HL] $ERROR DE HL B,$COMP CY RTN
16
CHAPTER 2 SOFTWARE BASICS
2.3 DECIMAL ADDITION The lowest addresses for decimal addition are specified in the DE and HL registers. The number of digits specified in BYTNUM are added. The addition result is saved in the area pointed to by the HL register. When the addition result is an overflow or an underflow, the processing branches to error processing. Have the branch address defined as `ERROR' in main program and make it a public declaration. Figure 2-3. Decimal Addition
Address DE+ BYTNUM-1 Address HL+ BYTNUM-1 Address HL+ BYTNUM-1
+
DE HL
=
HL
(1) Flowchart
BCDADD
CNumber of bytes in the decimal addition
BC-1 Number of bytes in the decimal addition not including the sign
BCDAD2
Do the augend and the addend have the same signs? Yes Decimal addition
No
Decimal subtraction
RET
17
78K/0 SERIES APPLICATION NOTE
DADDS CY0 Sign flag SFLAG0 DADDS1 A[DE]+[HL]+CY Add both the addend and augend to CY. The result is decimal-adjusted and saved in memory.
DEDE+1, HLHL+1 Increment the addend and augend addresses.
BB-1 No
B=0 Yes A[DE]+[HL]+CY Add both the addend and augend to CY. No
CY=1 Yes Sign flag SFLAG1 CY=0 DADDS3 Decimal-adjust the result.
CY=1 No A7=1 No Sign flag SFLAG=1 Yes A71 DADDS6 Save A in memory RET
Yes
Yes
No
ERROR
18
CHAPTER 2 SOFTWARE BASICS
DSUBS
Make the subtrahend positive. Sign flag0 No
Minuend<0 Yes Make the subtrahend positive. Sign flag1 DSUBS1 BC, CY0 DSUBS2
A[DE] - [HL] - CY Subtract CY from the minuend minus the subtrahend. DEDE+1, HLHL+1 Increment the minuend and subtrahend addresses
The result is decimal-adjusted and saved in memory.
CC-1 No
C=0 Yes CY=1 Yes Invert the sign flag by taking the 10's complement. DSUBS5 Result=0 No Sign flag=1 Yes Assign a negative sign to the result. No Yes No
RET
19
78K/0 SERIES APPLICATION NOTE
(2) Registers used AX, BC, DE, HL (3) Program listing ;************************************************************ ; * ; Input parameters * ; HL register: start address of the addend * ; DE register: start address of the augend * ; Output parameters * ; HL register: start address of the operation result * ; * ;************************************************************ PUBLIC PUBLIC PUBLIC EXTRN EXTBIT ; BYTNUM EQU ; CSEG BCDADD: MOV BCDAD1: MOV MOV DEC BCDAD2: MOV XCHW XCHW XCHW XOR XCHW XCHW XCHW BT CALL RET BCDAD3: CALL RET 20 !DSUBS BCDADD,BCDAD1,BCDAD2 DADDS DSUBS ERROR ; Branch address for error processing SFLAG ; Sign flag 4 ; Set the number of operand digits
C,#BYTNUM A,C B,A B
; Set the number of operand digits in the C register.
A,[HL+BYTNUM-1] ; Read in the most significant bit (sign data) of the augend AX,DE AX,HL AX,DE A,[HL+BYTNUM-1] ; Read in the most significant bit (sign data) of the augend AX,HL AX,DE AX,HL A.7,$BCDAD3 !DADDS ; Do the signs agree? ELSE subtraction processing ; THEN addition processing
CHAPTER 2 SOFTWARE BASICS
;=========================================================== ; ***** Decimal Addition ***** ;=========================================================== DADDS: CLR1 CLR1 DADDS1: MOV ADDC ADJBA MOV INCW INCW DBNZ MOV ADDC DADDS2: BNC SET1 CLR1 DADDS3: ADJBA BNC $DADDS4 BR ERROR DADDS4: BF BR DADDS5: BF SET1 DADDS6: MOV RET [HL],A SFLAG,$DADDS6 A.7 ; Set sign A.7,$DADDS5 ERROR $DADDS3 SFLAG CY ; Negative addition ; THEN set in the negative state A,[DE] A,[HL] [HL],A HL DE B,$DADDS1 A,[DE] A,[HL] ; Start addition from the least significant digit CY SFLAG
; End addition of (number-of-operand-digits - 1)
21
78K/0 SERIES APPLICATION NOTE
;================================================================= ; ***** Decimal Subtraction ***** ;================================================================= DSUBS: PUSH CLR1 MOV CLR1 MOV XCHW XCHW XCHW MOV BF CLR1 MOV SET1 DSUBS1: XCHW XCHW XCHW MOV MOV CLR1 DSUBS2: MOV SUBC ADJBS MOV INCW INCW DBNZ BNC POP PUSH MOV MOV DSUBS3: MOV SUB ADJBS MOV INCW DBNZ A,#99H A,[HL] [HL],A HL C,$DSUBS3 ; Complement operation on the subtraction result ; (subtraction-result - 99H) A,[DE] A,[HL] [HL],A HL DE C,$DSUBS2 $DSUBS5 HL HL A,B C,A AX,HL AX,DE AX,HL A,C B,A CY HL SFLAG A,[HL+BYTNUM-1] A.7 [HL+BYTNUM-1],A AX,DE AX,HL AX,DE A,[HL+BYTNUM-1] A.7,$DSUBS1 A.7 [HL+BYTNUM-1],A SFLAG
; Set the subtrahend to positive value.
; The minuend is negative. ; THEN set the minuend to a positive value. ; Set the sign to negative.
; End of the subtraction of the number of operand digits. ; THEN subtrahend > minuend
POP PUSH SET1 MOV MOV
HL HL CY A,B C,A
22
CHAPTER 2 SOFTWARE BASICS
DSUBS4: MOV ADDC ADJBA A,#0 A,[HL] ; Add 1 to the complement operation result.
MOV [HL],A INCW HL DBNZ C,$DSUBS4 MOV1 CY,SFLAG NOT1 CY MOV1 SFLAG,CY ;==================================================== ; ***** 0 Check of Operation Result ***** ;==================================================== DSUBS5: MOV MOV POP PUSH MOV DSUBS6: CMP INCW BNZ DBNZ POP RET DSUBS7: BF POP PUSH MOV SET1 MOV DSUBS8: POP RET HL SFLAG,$DSUBS8 ; Subtraction result is negative. HL ; THEN set sign HL A,[HL+BYTNUM-1] A.7 [HL+BYTNUM-1],A A,[HL] HL $DSUBS7 C,$DSUBS6 HL ; 0 check from the low-order digit A,B C,A HL HL A,#0
; End of checking all digits for 0 ; THEN subtraction result = 0
23
78K/0 SERIES APPLICATION NOTE
2.4 DECIMAL SUBTRACTION The lowest addresses for decimal subtraction are set in the DE and HL registers. Subtraction is performed on the number of digits specified in BYTNUM. The subtraction result is saved in the area specified in the HL register. Additionally, when the subtraction result is an overflow or an underflow, the processing branches to error processing. Have the branch address defined as `ERROR' in main program and make it a public declaration. This program replaces the augend and addend with the minuend and subtrahend respectively, and calls the decimal addition program. Figure 2-4. Decimal Subtraction
Address DE+ BYTNUM-1 Address HL BYTNUM-1 Address HL+ BYTNUM-1
-
DE HL
=
HL
(1) Flowchart
BCDSUB
CNumber of bytes in the decimal subtraction
Invert the sign bit of the subtrahend.
The subtrahend and minuend act as the addend and augend in decimal addition.
RET
(2) Registers used AX, BC, DE, HL
24
CHAPTER 2 SOFTWARE BASICS
(3) Program listing ;************************************************************ ; Input parameters * ; HL register: start address of the subtrahend * ; DE register: start address of the minuend * ; Output parameters * ; HL register: start address of the operation result * ; * ;************************************************************ PUBLIC BYTNUM PUBLIC BCDSUB EXTRN BCDADD,BCDAD2 ; BYTNUM EQU ; CSEG BCDSUB: MOV BCDSU1: MOV MOV DEC MOV addition. MOV1 NOT1 MOV1 MOV CALL RET CY,A.7 CY A.7,CY [HL+BYTNUM-1].A !BCDAD2 ; Invert the sign data. 4 ; Set the number of operand digits
C,#BYTNUM A,C B,A B A,[HL+BYTNUM-1]
; Set the number of operand digits in the C register.
; Set the most significant bit (sign data) of the subtrahend for use in
; Call decimal addition processing.
25
78K/0 SERIES APPLICATION NOTE
2.5 BINARY-TO-DECIMAL CONVERSION 16-bit binary data in the data memory is converted into 5-digit decimal data and saved in the data memory. The 16-bit binary data are divided by the decimal number 10 (4 times) and the conversion is based on the values of the results and remainders of these operations. Figure 2-5. Binary-to-Decimal Conversion
Low x x x High x Low 0 x 0 x 0 x 0 x 0 High x
16-bit binary (2 bytes)
5-digit decimal (5 bytes)
Example FFH is converted into decimal.
Low F F 0 High 0 Low 0 5 0 5 0 2 0 0 0 High 0
16-bit binary (2 bytes)
5-digit decimal (5 bytes)
(1) Registers used AX, BC, HL
26
CHAPTER 2 SOFTWARE BASICS
(2) Program listing PUBLIC B_DCONV DATDEC EQU 10 DSEG DS DS SADDRP 2 5 4
REGA: REGB:
; Save 16-bit binary data. ; Save 5-digit decimal data.
COLUMN EQU B_DCONV: MOVW MOV MOVW B_D1: MOV DIVUW XCH MOV INCW XCH DBNZ MOV MOV RET
AX,REGA B,#COLNUM HL,#REGB C,#DATDEC C A,C [HL],A HL A,C B,$B_D1 A,X [HL],A
27
78K/0 SERIES APPLICATION NOTE
2.6 BIT OPERATION MANIPULATION INSTRUCTION The logical product (AND) of the 1-bit flag in data memory and bit 4 in port 6 is taken. The logical sum (OR) of the result and bit 5 of port 6 is output to bit 6 of port 6. Figure 2-6. Bit Operation
FLG PORT6.4 PORT6.5
PORT6.6
(1) Program listing PUBLIC BSEG DBIT BIT_OP,FLG
FLG BIT_OP:
MOV1 AND1 OR1 MOV1 RET
CY,FLG CY,P6.4 CY,P6.5 P6.6,CY
28
CHAPTER 2 SOFTWARE BASICS
2.7 BINARY MULTIPLICATION (16 BITS x 16 BITS) The data in the multiplicand area (HIKAKE; 16 bits) and the multiplier area (KAKE; 16 bits) are multiplied. The result is saved in the operation result storage area (KOTAE). Figure 2-7. Binary Multiplication
HIKAKE+1 Multiplicand area (2 bytes) x KAKE+1 Multiplier area (2 bytes) KAKE HIKAKE
=
KOTAE+3 Operation result storage area (4 bytes)
KOTAE
Multiplication is implemented by adding the multiplicand only the number of "1" bits in the multiplier.
29
78K/0 SERIES APPLICATION NOTE
|
